/*
 * Copyright (c) 2006-2018, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author            Notes
 * 2018-11-06     balanceTWK        first version
 * 2019-04-23     WillianChan       Fix GPIO serial number disorder
 */

#include <rtdevice.h>
#include <rthw.h>
#include <stm32f4xx_exti.h>
#include <stm32f4xx_syscfg.h>
#include <stm32f4xx_gpio.h>
#include <misc.h>

#define GET_PIN(PORTx, PIN) (rt_base_t)((16 * (((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA) / (0x0400UL))) + PIN)

#define __STM32_PIN(index, gpio, gpio_index)     \
    {                                            \
        index, GPIO##gpio, GPIO_Pin_##gpio_index \
    }

#define __STM32_PIN_RESERVE \
    {                       \
        -1, 0, 0            \
    }

/* STM32 GPIO driver */
struct pin_index
{
    int index;
    GPIO_TypeDef *gpio;
    uint32_t pin;
};

#ifdef RT_USING_PIN

#define RT_USING_GPIOA
#define RT_USING_GPIOB
#define RT_USING_GPIOC
#define RT_USING_GPIOD
#define RT_USING_GPIOE
// #define RT_USING_GPIOF
// #define RT_USING_GPIOG
// #define RT_USING_GPIOH
// #define RT_USING_GPIOI
// #define RT_USING_GPIOJ
// #define RT_USING_GPIOK

static const struct pin_index pins[] =
    {
#ifdef RT_USING_GPIOA
        __STM32_PIN(0, A, 0),
        __STM32_PIN(1, A, 1),
        __STM32_PIN(2, A, 2),
        __STM32_PIN(3, A, 3),
        __STM32_PIN(4, A, 4),
        __STM32_PIN(5, A, 5),
        __STM32_PIN(6, A, 6),
        __STM32_PIN(7, A, 7),
        __STM32_PIN(8, A, 8),
        __STM32_PIN(9, A, 9),
        __STM32_PIN(10, A, 10),
        __STM32_PIN(11, A, 11),
        __STM32_PIN(12, A, 12),
        __STM32_PIN(13, A, 13),
        __STM32_PIN(14, A, 14),
        __STM32_PIN(15, A, 15),
#endif
#ifdef RT_USING_GPIOB
        __STM32_PIN(16, B, 0),
        __STM32_PIN(17, B, 1),
        __STM32_PIN(18, B, 2),
        __STM32_PIN(19, B, 3),
        __STM32_PIN(20, B, 4),
        __STM32_PIN(21, B, 5),
        __STM32_PIN(22, B, 6),
        __STM32_PIN(23, B, 7),
        __STM32_PIN(24, B, 8),
        __STM32_PIN(25, B, 9),
        __STM32_PIN(26, B, 10),
        __STM32_PIN(27, B, 11),
        __STM32_PIN(28, B, 12),
        __STM32_PIN(29, B, 13),
        __STM32_PIN(30, B, 14),
        __STM32_PIN(31, B, 15),
#endif
#ifdef RT_USING_GPIOC
        __STM32_PIN(32, C, 0),
        __STM32_PIN(33, C, 1),
        __STM32_PIN(34, C, 2),
        __STM32_PIN(35, C, 3),
        __STM32_PIN(36, C, 4),
        __STM32_PIN(37, C, 5),
        __STM32_PIN(38, C, 6),
        __STM32_PIN(39, C, 7),
        __STM32_PIN(40, C, 8),
        __STM32_PIN(41, C, 9),
        __STM32_PIN(42, C, 10),
        __STM32_PIN(43, C, 11),
        __STM32_PIN(44, C, 12),
        __STM32_PIN(45, C, 13),
        __STM32_PIN(46, C, 14),
        __STM32_PIN(47, C, 15),
#endif
#ifdef RT_USING_GPIOD
        __STM32_PIN(48, D, 0),
        __STM32_PIN(49, D, 1),
        __STM32_PIN(50, D, 2),
        __STM32_PIN(51, D, 3),
        __STM32_PIN(52, D, 4),
        __STM32_PIN(53, D, 5),
        __STM32_PIN(54, D, 6),
        __STM32_PIN(55, D, 7),
        __STM32_PIN(56, D, 8),
        __STM32_PIN(57, D, 9),
        __STM32_PIN(58, D, 10),
        __STM32_PIN(59, D, 11),
        __STM32_PIN(60, D, 12),
        __STM32_PIN(61, D, 13),
        __STM32_PIN(62, D, 14),
        __STM32_PIN(63, D, 15),
#endif
#ifdef RT_USING_GPIOE
        __STM32_PIN(64, E, 0),
        __STM32_PIN(65, E, 1),
        __STM32_PIN(66, E, 2),
        __STM32_PIN(67, E, 3),
        __STM32_PIN(68, E, 4),
        __STM32_PIN(69, E, 5),
        __STM32_PIN(70, E, 6),
        __STM32_PIN(71, E, 7),
        __STM32_PIN(72, E, 8),
        __STM32_PIN(73, E, 9),
        __STM32_PIN(74, E, 10),
        __STM32_PIN(75, E, 11),
        __STM32_PIN(76, E, 12),
        __STM32_PIN(77, E, 13),
        __STM32_PIN(78, E, 14),
        __STM32_PIN(79, E, 15),
#endif
#ifdef RT_USING_GPIOF
        __STM32_PIN(80, F, 0),
        __STM32_PIN(81, F, 1),
        __STM32_PIN(82, F, 2),
        __STM32_PIN(83, F, 3),
        __STM32_PIN(84, F, 4),
        __STM32_PIN(85, F, 5),
        __STM32_PIN(86, F, 6),
        __STM32_PIN(87, F, 7),
        __STM32_PIN(88, F, 8),
        __STM32_PIN(89, F, 9),
        __STM32_PIN(90, F, 10),
        __STM32_PIN(91, F, 11),
        __STM32_PIN(92, F, 12),
        __STM32_PIN(93, F, 13),
        __STM32_PIN(94, F, 14),
        __STM32_PIN(95, F, 15),
#endif
#ifdef RT_USING_GPIOG
        __STM32_PIN(96, G, 0),
        __STM32_PIN(97, G, 1),
        __STM32_PIN(98, G, 2),
        __STM32_PIN(99, G, 3),
        __STM32_PIN(100, G, 4),
        __STM32_PIN(101, G, 5),
        __STM32_PIN(102, G, 6),
        __STM32_PIN(103, G, 7),
        __STM32_PIN(104, G, 8),
        __STM32_PIN(105, G, 9),
        __STM32_PIN(106, G, 10),
        __STM32_PIN(107, G, 11),
        __STM32_PIN(108, G, 12),
        __STM32_PIN(109, G, 13),
        __STM32_PIN(110, G, 14),
        __STM32_PIN(111, G, 15),
#endif
#ifdef RT_USING_GPIOH
        __STM32_PIN(112, H, 0),
        __STM32_PIN(113, H, 1),
        __STM32_PIN(114, H, 2),
        __STM32_PIN(115, H, 3),
        __STM32_PIN(116, H, 4),
        __STM32_PIN(117, H, 5),
        __STM32_PIN(118, H, 6),
        __STM32_PIN(119, H, 7),
        __STM32_PIN(120, H, 8),
        __STM32_PIN(121, H, 9),
        __STM32_PIN(122, H, 10),
        __STM32_PIN(123, H, 11),
        __STM32_PIN(124, H, 12),
        __STM32_PIN(125, H, 13),
        __STM32_PIN(126, H, 14),
        __STM32_PIN(127, H, 15),
#endif
#ifdef RT_USING_GPIOI
        __STM32_PIN(128, I, 0),
        __STM32_PIN(129, I, 1),
        __STM32_PIN(130, I, 2),
        __STM32_PIN(131, I, 3),
        __STM32_PIN(132, I, 4),
        __STM32_PIN(133, I, 5),
        __STM32_PIN(134, I, 6),
        __STM32_PIN(135, I, 7),
        __STM32_PIN(136, I, 8),
        __STM32_PIN(137, I, 9),
        __STM32_PIN(138, I, 10),
        __STM32_PIN(139, I, 11),
        __STM32_PIN(140, I, 12),
        __STM32_PIN(141, I, 13),
        __STM32_PIN(142, I, 14),
        __STM32_PIN(143, I, 15),
#endif
#ifdef RT_USING_GPIOJ
        __STM32_PIN(144, J, 0),
        __STM32_PIN(145, J, 1),
        __STM32_PIN(146, J, 2),
        __STM32_PIN(147, J, 3),
        __STM32_PIN(148, J, 4),
        __STM32_PIN(149, J, 5),
        __STM32_PIN(150, J, 6),
        __STM32_PIN(151, J, 7),
        __STM32_PIN(152, J, 8),
        __STM32_PIN(153, J, 9),
        __STM32_PIN(154, J, 10),
        __STM32_PIN(155, J, 11),
        __STM32_PIN(156, J, 12),
        __STM32_PIN(157, J, 13),
        __STM32_PIN(158, J, 14),
        __STM32_PIN(159, J, 15),
#endif
#ifdef RT_USING_GPIOK
        __STM32_PIN(160, K, 0),
        __STM32_PIN(161, K, 1),
        __STM32_PIN(162, K, 2),
        __STM32_PIN(163, K, 3),
        __STM32_PIN(164, K, 4),
        __STM32_PIN(165, K, 5),
        __STM32_PIN(166, K, 6),
        __STM32_PIN(167, K, 7),
        __STM32_PIN(168, K, 8),
        __STM32_PIN(169, K, 9),
        __STM32_PIN(170, K, 10),
        __STM32_PIN(171, K, 11),
        __STM32_PIN(172, K, 12),
        __STM32_PIN(173, K, 13),
        __STM32_PIN(174, K, 14),
        __STM32_PIN(175, K, 15),
#endif

};

/* STM32 GPIO irq information */
struct pin_irq
{
    /* EXTI port source gpiox, such as EXTI_PortSourceGPIOA */
    rt_uint8_t port_source;
    /* EXTI pin sources, such as EXTI_PinSource0 */
    rt_uint8_t pin_source;
    /* NVIC IRQ EXTI channel, such as EXTI0_IRQn */
    IRQn_Type irq_exti_channel;
    /* EXTI line, such as EXTI_Line0 */
    rt_uint32_t exti_line;
};

static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
    {
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
        {-1, 0, RT_NULL, RT_NULL},
};

__STATIC_INLINE void Set(const struct pin_index *pin) { pin->gpio->BSRRL = pin->pin; }
__STATIC_INLINE void Clear(const struct pin_index *pin) { pin->gpio->BSRRH = pin->pin; }
__STATIC_INLINE void Write(const struct pin_index *pin, rt_base_t value) { value ? Set(pin) : Clear(pin); }
__STATIC_INLINE int Read(const struct pin_index *pin) { return ((pin->gpio->IDR) & pin->pin); }

#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static const struct pin_index *get_pin(uint8_t pin)
{
    const struct pin_index *index;

    if (pin < ITEM_NUM(pins))
    {
        index = &pins[pin];
        if (index->index == -1)
            index = RT_NULL;
    }
    else
    {
        index = RT_NULL;
    }

    return index;
};

static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
    const struct pin_index *index;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return;
    }
    Write(index, value);
}

static int stm32_pin_read(rt_device_t dev, rt_base_t pin)
{
    int value;
    const struct pin_index *index;

    value = PIN_LOW;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return value;
    }

    value = Read(index);

    return value;
}

static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
    const struct pin_index *index;
    GPIO_InitTypeDef GPIO_InitStruct;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return;
    }

    /* Configure GPIO_InitStructure */
    GPIO_InitStruct.GPIO_Pin = index->pin;
    GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
    GPIO_InitStruct.GPIO_Speed = GPIO_Speed_25MHz;
    GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;

    if (mode == PIN_MODE_OUTPUT)
    {
        /* output setting */
        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
        GPIO_InitStruct.GPIO_OType = GPIO_OType_PP;
        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
    }
    else if (mode == PIN_MODE_INPUT)
    {
        /* input setting: not pull. */
        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
    }
    else if (mode == PIN_MODE_INPUT_PULLUP)
    {
        /* input setting: pull up. */
        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP;
    }
    else if (mode == PIN_MODE_INPUT_PULLDOWN)
    {
        /* input setting: pull down. */
        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_DOWN;
    }
    else if (mode == PIN_MODE_OUTPUT_OD)
    {
        /* output setting: od. */
        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
        GPIO_InitStruct.GPIO_OType = GPIO_OType_OD;
        GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
    }

    GPIO_Init(index->gpio, &GPIO_InitStruct);
}

rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
    int i;
    for (i = 0; i < 32; i++)
    {
        if ((0x01 << i) == bit)
        {
            return i;
        }
    }
    return -1;
}

rt_inline rt_int32_t bitno2bit(rt_uint32_t bitno)
{
    if (bitno <= 32)
    {
        return 1UL << bitno;
    }
    else
    {
        return 0;
    }
}

const struct pin_irq *get_pin_irq(uint16_t pin)
{
    static struct pin_irq irq;
    const struct pin_index *index;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return RT_NULL;
    }

    irq.exti_line = index->pin;
    irq.pin_source = bit2bitno(index->pin);
    irq.port_source = ((uint32_t)index->gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE);
    switch (irq.pin_source)
    {
    case 0:
        irq.irq_exti_channel = EXTI0_IRQn;
        break;
    case 1:
        irq.irq_exti_channel = EXTI1_IRQn;
        break;
    case 2:
        irq.irq_exti_channel = EXTI2_IRQn;
        break;
    case 3:
        irq.irq_exti_channel = EXTI3_IRQn;
        break;
    case 4:
        irq.irq_exti_channel = EXTI4_IRQn;
        break;
    case 5:
    case 6:
    case 7:
    case 8:
    case 9:
        irq.irq_exti_channel = EXTI9_5_IRQn;
        break;
    case 10:
    case 11:
    case 12:
    case 13:
    case 14:
    case 15:
        irq.irq_exti_channel = EXTI15_10_IRQn;
        break;
    default:
        return RT_NULL;
    }

    return &irq;
};

static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
    const struct pin_index *index;
    rt_base_t level;

    rt_int32_t irqindex = -1;
    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return -RT_ENOSYS;
    }
    irqindex = bit2bitno(index->pin);
    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab))
    {
        return -RT_ENOSYS;
    }

    level = rt_hw_interrupt_disable();
    if (pin_irq_hdr_tab[irqindex].pin == pin &&
        pin_irq_hdr_tab[irqindex].hdr == hdr &&
        pin_irq_hdr_tab[irqindex].mode == mode &&
        pin_irq_hdr_tab[irqindex].args == args)
    {
        rt_hw_interrupt_enable(level);
        return RT_EOK;
    }
    if (pin_irq_hdr_tab[irqindex].pin != -1)
    {
        rt_hw_interrupt_enable(level);
        return -RT_EBUSY;
    }
    pin_irq_hdr_tab[irqindex].pin = pin;
    //TODO PA1 will overwrite PB1's hdr, using rt_list ?
    pin_irq_hdr_tab[irqindex].hdr = hdr;
    pin_irq_hdr_tab[irqindex].mode = mode;
    pin_irq_hdr_tab[irqindex].args = args;
    rt_hw_interrupt_enable(level);

    return RT_EOK;
}

static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
    const struct pin_index *index;
    rt_base_t level;
    rt_int32_t irqindex = -1;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return -RT_ENOSYS;
    }
    irqindex = bit2bitno(index->pin);
    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab))
    {
        return -RT_ENOSYS;
    }

    level = rt_hw_interrupt_disable();
    if (pin_irq_hdr_tab[irqindex].pin == -1)
    {
        rt_hw_interrupt_enable(level);
        return RT_EOK;
    }
    pin_irq_hdr_tab[irqindex].pin = -1;
    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
    pin_irq_hdr_tab[irqindex].mode = 0;
    pin_irq_hdr_tab[irqindex].args = RT_NULL;
    rt_hw_interrupt_enable(level);

    return RT_EOK;
}

static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
                                     rt_uint32_t enabled)
{
    const struct pin_index *index;
    const struct pin_irq *irq;
    rt_base_t level;
    rt_int32_t irqindex = -1;
    NVIC_InitTypeDef NVIC_InitStructure;
    EXTI_InitTypeDef EXTI_InitStructure;

    index = get_pin(pin);
    if (index == RT_NULL)
    {
        return -RT_ENOSYS;
    }
    if (enabled == PIN_IRQ_ENABLE)
    {
        irqindex = bit2bitno(index->pin);
        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab))
        {
            return -RT_ENOSYS;
        }
        level = rt_hw_interrupt_disable();
        if (pin_irq_hdr_tab[irqindex].pin == -1)
        {
            rt_hw_interrupt_enable(level);
            return -RT_ENOSYS;
        }

        irq = get_pin_irq(pin);
        if (irq == RT_NULL)
        {
            rt_hw_interrupt_enable(level);
            return -RT_ENOSYS;
        }
        /* select the input source pin for the EXTI line */
        SYSCFG_EXTILineConfig(irq->port_source, irq->pin_source);
        /* select the mode(interrupt, event) and configure the trigger selection */
        EXTI_InitStructure.EXTI_Line = irq->exti_line;
        EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
        switch (pin_irq_hdr_tab[irqindex].mode)
        {
        case PIN_IRQ_MODE_RISING:
            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
            break;
        case PIN_IRQ_MODE_FALLING:
            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
            break;
        case PIN_IRQ_MODE_RISING_FALLING:
            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
            break;
        }
        EXTI_InitStructure.EXTI_LineCmd = ENABLE;
        EXTI_Init(&EXTI_InitStructure);
        /* configure NVIC IRQ channel mapped to the EXTI line */
        NVIC_InitStructure.NVIC_IRQChannel = irq->irq_exti_channel;
        NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
        NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
        NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
        NVIC_Init(&NVIC_InitStructure);

        rt_hw_interrupt_enable(level);
    }
    else if (enabled == PIN_IRQ_DISABLE)
    {
        irq = get_pin_irq(pin);
        if (irq == RT_NULL)
        {
            return -RT_ENOSYS;
        }
        EXTI_InitStructure.EXTI_Line = irq->exti_line;
        EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
        EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
        EXTI_InitStructure.EXTI_LineCmd = DISABLE;
        EXTI_Init(&EXTI_InitStructure);
    }
    else
    {
        return -RT_ENOSYS;
    }

    return RT_EOK;
}
const static struct rt_pin_ops _stm32_pin_ops =
    {
        .pin_mode = stm32_pin_mode,
        .pin_write = stm32_pin_write,
        .pin_read = stm32_pin_read,
        .pin_attach_irq = stm32_pin_attach_irq,
        .pin_detach_irq = stm32_pin_dettach_irq,
        .pin_irq_enable = stm32_pin_irq_enable,
};

static int stm32_gpio_register(void)
{
    return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
}
INIT_BOARD_EXPORT(stm32_gpio_register);

rt_inline void pin_irq_hdr(int irqno)
{
    EXTI_ClearITPendingBit(bitno2bit(irqno));
    if (pin_irq_hdr_tab[irqno].hdr)
    {
        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
    }
}

void EXTI0_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();
    pin_irq_hdr(0);
    /* leave interrupt */
    rt_interrupt_leave();
}

void EXTI1_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();
    pin_irq_hdr(1);
    /* leave interrupt */
    rt_interrupt_leave();
}

void EXTI2_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();
    pin_irq_hdr(2);
    /* leave interrupt */
    rt_interrupt_leave();
}

void EXTI3_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();
    pin_irq_hdr(3);
    /* leave interrupt */
    rt_interrupt_leave();
}

void EXTI4_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();
    pin_irq_hdr(4);
    /* leave interrupt */
    rt_interrupt_leave();
}

void EXTI9_5_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();
    if (EXTI_GetITStatus(EXTI_Line5) != RESET)
    {
        pin_irq_hdr(5);
    }
    if (EXTI_GetITStatus(EXTI_Line6) != RESET)
    {
        pin_irq_hdr(6);
    }
    if (EXTI_GetITStatus(EXTI_Line7) != RESET)
    {
        pin_irq_hdr(7);
    }
    if (EXTI_GetITStatus(EXTI_Line8) != RESET)
    {
        pin_irq_hdr(8);
    }
    if (EXTI_GetITStatus(EXTI_Line9) != RESET)
    {
        pin_irq_hdr(9);
    }
    /* leave interrupt */
    rt_interrupt_leave();
}

void EXTI15_10_IRQHandler(void)
{
    /* enter interrupt */
    rt_interrupt_enter();
    if (EXTI_GetITStatus(EXTI_Line10) != RESET)
    {
        pin_irq_hdr(10);
    }
    if (EXTI_GetITStatus(EXTI_Line11) != RESET)
    {
        pin_irq_hdr(11);
    }
    if (EXTI_GetITStatus(EXTI_Line12) != RESET)
    {
        pin_irq_hdr(12);
    }
    if (EXTI_GetITStatus(EXTI_Line13) != RESET)
    {
        pin_irq_hdr(13);
    }
    if (EXTI_GetITStatus(EXTI_Line14) != RESET)
    {
        pin_irq_hdr(14);
    }
    if (EXTI_GetITStatus(EXTI_Line15) != RESET)
    {
        pin_irq_hdr(15);
    }
    /* leave interrupt */
    rt_interrupt_leave();
}

#endif
